Synopsys Inc. has deepened its partnership with Taiwan Semiconductor Manufacturing Co. (TSMC), rolling out an array of new design software, interface IP, and analysis tools tailored for TSMC's most advanced process nodes. The expanded collaboration, announced during TSMC's North America Technology Symposium in Santa Clara, targets the growing complexity of AI chip design and verification.
The new tools support TSMC's 3-nanometer, 2-nanometer, A16, and A14 manufacturing processes, as well as advanced packaging technologies. Synopsys said its 3DIC Compiler now integrates directly with RedHawk-SC, RedHawk-SC Electrothermal, and Ansys HFSS tools to enable comprehensive thermal, power, and high-speed signal analysis—critical for AI chips that combine chiplets, advanced packaging, and high-bandwidth connections.
Market Reaction
Synopsys shares rebounded to $483.00 early Friday, recovering from a 4.28% decline on Thursday that ended an eight-day winning streak and left the stock at $456.85. The company's market capitalization now stands at approximately $92 billion.
Michael Buehler-Garcia, senior vice president at Synopsys, highlighted that TSMC's newest process and packaging technologies are "opening new frontiers" for performance, bandwidth, and energy efficiency. Aveek Sarkar, who heads ecosystem and alliance management at TSMC, described the collaboration as a response to "rapidly growing demands" in AI and high-performance computing.
Industry-Wide Race
Synopsys is not alone in pursuing TSMC's latest nodes. Cadence Design Systems has broadened its TSMC tie-up to span N3, N2, A16, and A14 process technologies, while Siemens reported certifications for its electronic design automation (EDA) tools across multiple advanced nodes, including A16 and A14. The EDA market—software used to design and verify chips before fabrication—remains intensely competitive.
TSMC used the symposium to unveil the A13 process, a tighter version of its A14 node, with production slated for 2029. The chipmaker also detailed expanded plans for its CoWoS advanced-packaging technology and introduced COUPE, a co-packaged optics solution aimed at accelerating data movement in AI data centers, with production targeted for 2026.
Post-Ansys Integration
Synopsys is working to integrate Ansys into its core chip design business after closing the $35 billion acquisition in July 2025. The deal brought simulation software capable of modeling heat, electromagnetic interference, and mechanical stress—key factors in real-world chip performance. Last month, Reuters reported that Synopsys began launching new software tools leveraging Ansys capabilities.
Financially, Synopsys reported first-quarter fiscal 2026 revenue of $2.409 billion, up from $1.455 billion a year earlier, and expects full-year revenue between $9.56 billion and $9.66 billion. However, GAAP net income fell to $65.0 million from $295.7 million, weighed down by amortization, stock-based compensation, and restructuring expenses. CFO Shelagh Glaser described the quarter as reflecting "strong execution."
The company faces higher post-acquisition costs and, in November, Reuters reported plans to cut about 10% of its workforce—close to 2,000 positions—as it shifts spending priorities. Its guidance also assumes no new export-control or U.S. Entity List moves, highlighting ongoing China policy risks for chip software providers.
Despite these headwinds, the latest TSMC update strengthens Synopsys' position in AI hardware. As TSMC moves to more advanced nodes and larger chip packages, toolmakers that catch design glitches sooner gain pricing leverage, while those with smoother workflows can outpace rivals.
